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mt9v131: 1/4-inch soc vga cmos digital image sensor features mt9v131_ds rev. h 4/15 en 1 ?semiconductor components industries, llc,2015 1/4-inch soc vga cmos digital image sensor mt9v131 datasheet, rev. h for the latest datasheet revision, please visit www.onsemi.com features ? system-on-a-chip (soc)?completely integrated camera system ? ultra low-power, cost effective cmos image sensor ? superior low-light performance ? up to 30 fps progressive scan at 27 mhz for high- quality video at vga resolution ? on-chip image flow processor (ifp) performs sophisticated processing: color recovery and correction, sharpening, gamma, lens shading correction, on-the-fly defect correction, 2x fixed zoom ? image decimation to arbi trary size with smooth, continuous zoom and pan ? automatic exposure, white balance and black compensation, flicker avoidance, color saturation, and defect identification and correction, auto frame rate, back light compensation ? xenon and led-type flash support ? two-wire serial programming interface ? progressive itu_r bt.656 (ycbcr), yuv, 565rgb, 555rgb, and 444rgb output data formats applications ?security ?biometrics ?toys general description the on semiconductor mt9v131 is a 1/4-inch vga- format cmos active-pixel digital image sensor, the result of combining the mt9v011 image sensor core with on semiconductor's third-generation digital image flow processor technology. the mt9v131 has an active imaging pixel array of 649 x 489, capturing high- quality color images at vga resolution. the sensor is a complete camera-on-a-chip solution and is designed specifically to meet the demands of products such as surveillance cameras. it incorporates sophisticated camera functions on-chip and is pro- grammable through a simple two-wire serial interface. table 1: key performance parameters parameter typical value optical format 1/4-inch (4:3) active imager size 3.58 mm (h) x 2.69 mm (v) 4.48 mm (diagonal) active pixels 640h x 480v (vga) pixel size 5.6 ? m x 5.6 ?? m color filter array rgb bayer pattern shutter type electronic rolling shutter (ers) maximum data rate master clock 12 ? 13.5 mp/s 24 ? 27 mhz frame rate vga (640 x 480) 15 fps at 12 mhz (default), programmable up to 30 fps at 27 mhz cif (352 x 288) programmable up to 60 fps qvga (320 x 240) programmable up to 90 fps adc resolution 10-bit, on-chip responsivity 1.9 v/lux-sec (550nm) dynamic range 60 db snr max 45 db supply voltage 2.8 v + 0.25 v power consumption <80 mw at 2.8 v, 15 fps at 12 mhz operating temperature -20c to +70c packaging 48-pin clcc
mt9v131_ds rev. h 4/15 en 2 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor ordering information ordering information table 2: available part numbers part number product description orderable product attribute description mt9v131c12stc-dr vga 1/4" soc dry pack without protective film MT9V131C12STC-TR vga 1/4" soc tape & reel without protective film
mt9v131_ds rev. h 4/15 en 3 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 image flow processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 output data ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 sensor core overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 propagation delays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 appendix a ? sensor timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 serial bus description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 two-wire serial interface sam plewriteandreadsequences (with saddr = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 appendix b ? overview of programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
mt9v131_ds rev. h 4/15 en 4 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor list of figures list of figures figure 1: chip block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 2: internal register grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 3: typical configuration (connection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 4: 48-pin clcc pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 5: image flow processor bl ock diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 6: sensor core block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 7: pixel array description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 8: pixel color pattern detail (top right corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 9: spatial illustration of image re adout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 10: propagation delays for pixclk and data out signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 11: propagation delays for frame_vali d and line_valid signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 7 figure 12: data output timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 13: typical spectral char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 14: die center ? image center offs et . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 15: chief ray angle (cra) vs. image height . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 16: row timing and frame_valid/line_valid signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 17: timing diagram showing a write to r0x09 with value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 18: timing diagram showing a read from r0x09; returned value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 19: timing diagram showing a bytewise write to r0x09 with value 0x0284. . . . . . . . . . . . . . . . . . . . . . . .25 figure 20: timing diagram showing a bytewise read from r0x 09; returned value 0x0284 . . . . . . . . . . . . . . . .25 figure 21: serial host interface start condition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 22: serial host interface stop condition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 23: serial host interface data timing for write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 24: serial host interface data timing for read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 25: acknowledge signal timing after an 8-bit write to th e sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 26: acknowledge signal timing after an 8-bit read from th e sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 27: 48- pin clcc package ou tline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
mt9v131_ds rev. h 4/15 en 5 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor list of tables list of tables table 1: key performance parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3: pin description for the clcc package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 4: yuv/ycbcr output data ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 5: rgb output data ordering in default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 6: byte ordering in 8 + 2 bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 7: dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 8: ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 9: frame time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 10: frame time ? larger than one frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 11: non-default register settings optimizing 15 fps at 12 mhz operation . . . . . . . . . . . . . . . . . . . . . . . .28 table 12: non-default register settings optimizing 30 fps at 27 mhz operation . . . . . . . . . . . . . . . . . . . . . . . .28 table 13: relation between ifp r0x37[9:5] se tting and frame rate range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 14: decimation, zoom, and pan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 15: ycbcr settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 16: yuv settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
mt9v131_ds rev. h 4/15 en 6 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor general description general description this soc vga cmos image sensor features on semiconductor?s breakthrough, low- noise cmos imaging technology that achiev es ccd image quality (based on signal-to- noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and inte- gration advantages of cmos. the mt9v131 is a fully-automatic, single-chip camera, requiring only a power supply, lens, and clock source for basic operation. ou tput video is streamed through a parallel 8- bit d out port, as shown in figure 1. the output pixel clock is used to latch the data, while frame_valid (fv) and line_valid (lv) signals indicate the active video. the sensor can be put in an ultra-low power sleep mode by asserting the standby pin. output signals can also be tri-stated by de-asserting the oe_bar pin. the mt9v131 internal registers can be configured using a two-wire serial interface. the mt9v131 can be programmed to output progressive scan images up to 30 fps in an 8-bit itu_r bt.656 (ycbcr) formerly ccir656, yuv, 565rgb, 555rgb, or 444rgb formats. 10-bit raw bayer data output can al so be selected. the fv and lv signals are output on dedicated pins, along with a pixe l clock (pixclk) that is synchronous with valid data. figure 1: chip block diagram the mt9v131 can accept an input clock of up to 27 mhz, delivering 30 fps. with power-on defaults (see appendix b on page 28 for recommended defaults), the camera is configured to deliver 15 fps at 12 mhz and automatically slows down the frame rate in low-light conditions to achieve longer exposures and better image quality. internally, the mt9v131 consists of a sensor core and an image flow processor (ifp). the sensor core functions to capture raw bayer-encoded images that are input into the ifp as shown in figure 1. the ifp processes the incoming stream to create interpolated, color-corrected output and controls the sensor core to maintain the desirable exposure and color balance. sensor core and ifp registers are grouped into two separate address spaces, as shown in figure 2 on page 7. the internal registers can be accessed through the two-wire serial interface. selecting the desired address space can be accomplished by programming register r0x01, which remains present in both register sets. d out [7:0]:d out _lsb[1:0] pixclk frame_valid line_valid flash communication bus sensor core . based on mt9v011 . 668h x 496v (vga+ reference) . 1/4-inch optical format . auto black compensation . programmable analog gain . programmable exposure . low power, 10-bit adcs sram line buffers image flow processor . color correction, gamma, lens shading correction . auto exposure, white balance . interpolation and defect correction . flicker avoidance sclk s data s addr clk standby oe_bar v dd /d gnd v aa /a gnd v aa_ pix
mt9v131_ds rev. h 4/15 en 7 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor general description figure 2: internal register grouping note: program r0x01 to select the desired space (0b0100 = sensor core registers, 0b0001 = ifp/soc reg- isters). figure 3 shows mt9v131 typical connections. for low-noise operation, the mt9v131 requires separate supplies for analog and di gital power. incoming digital and analog ground conductors can be tied together righ t next to the die. both power supply rails should be decoupled to ground using capaci tors. the use of inductance filters is not recommended. figure 3: typical configuration (connection) note: on semiconductor recommends a 1.5k ? resistor value, but it may be greater for slower two-wire speed. r0x00 r0x01 sensor core registers (r0x02..r0xff ) r0x01 = 0b0100 r0x00 r0x01 ifp registers (r0x02..r0xff ) r0x01 = 0b0001 d out [7:0]:d out _lsb[1:0] frame_ vali d line_vali d pixclk flash to cmo s camera port d gnd a gnd to xenon flas h trigger or led enable v dd v aa 10f master clock two-wir e serial bus { { a gnd d gnd s addr reset_bar s data sclk extclk oe_bar standb y v dd v aa v aa _pix adc_test 1k 1.5k 1.5k dnu
mt9v131_ds rev. h 4/15 en 8 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor pin assignment pin assignment figure 4: 48-pin clcc pinout diagram 1 2 3 4 5 6 44 43 19 20 21 22 23 24 25 26 27 28 29 30 7 8 9 10 11 12 13 14 15 16 17 18 42 41 40 39 38 37 36 35 34 33 32 31 v dd d out 1 d out 0 d out _lsb1 d out_ lsb0 d gnd flash pixclk line_valid frame_valid v dd nc nc v dd v dd dnu d gnd v dd d gnd oe_bar standby reset_bar v aa _pix adc_test d gnd extclk sclk s data s addr d gnd v dd v aa a gnd v aa a gnd nc nc d gnd d out 2 d out 3 d out4 d out 5 d gnd v dd d out 6 d out 7 v dd d gnd 48 47 46 45
mt9v131_ds rev. h 4/15 en 9 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor pin assignment table 3: pin description for the clcc package pin number pin name type description 20 extclk input master clock into sensor. default is 12 mhz (27 mhz maximum). 21 sclk input serial clock. 23 s addr input serial interface address sele ct: r0xb8 when high (default). r0x90 when low. 31 adc_test input tie to vaa_pix (factory use only). 33 reset_bar input asynchronous reset of sensor when low. all registers assume factory defaults. 34 standby input when high, puts the im ager in ultra-low power standby mode. 35 oe_bar input output_enable pin. when high, tri-state all outputs except s data (tie low for normal operation). 39 dnu input tie to digital ground. 22 s data i/o serial data i/o. 13 flash output flash strobe. 14 pixclk output pixel clock out. pixel data output are valid during rising edge of this clock. ifp r0x08 [9] inverts polarity. frequency = master clock. 15 line_valid output active high during line of selectable valid pixel data. 16 frame_valid output active high during frame of valid pixel data. 45 d out 7 output itu_r bt.656/rgb data bit 7 (msb). 46 d out 6 output itu_r bt.656/rgb data bit 6. 1d out 5 output itu_r bt.656/rgb data bit 5. 2d out 4 output itu_r bt.656/rgb data bit 4. 3d out 3 output itu_r bt.656/rgb data bit 3. 4d out 2 output itu_r bt.656/rgb data bit 2. 8d out 1 output itu_r bt.656/rgb data bit 1. 9d out 0 output itu_r bt.656/rgb data bit 0 (lsb). 10 d out _lsb1 output raw bayer 10-bit output. 11 d out _lsb0 output raw bayer 10-bit output (lsb). 7, 17, 25, 37, 40, 41, 44, 47 v dd supply digital power (2.8v). 26, 28 v aa supply analog power (2.8v). 32 v aa _pix supply pixel array power (2.8v). 27, 29 a gnd supply analog ground. 5, 12, 19, 24, 36, 38, 43, 48 d gnd supply digital ground. 6, 18, 30, 42 nc C no connect.
mt9v131_ds rev. h 4/15 en 10 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor image flow processor image flow processor overview of architecture the ifp consists of a color processing pi peline and a measurement and control logic block, as shown in figure 5 on page 11. the st ream of raw data from the sensor enters the pipeline and undergoes a number of transformations. image stream processing starts from conditioning the black level an d applying a digital gain. the lens shading block compensates for signal loss caused by the lens. next, the data is interpolated to recover missing color components for each pi xel and defective pixels are corrected. the resulting interpolated rgb data passes through the current color correction matrix (ccm), gamma, and saturation corrections and is formatted for final output. the measurement and control logic continuo usly accumulates statistics about image brightness and color. indoor 50/60 hz flic ker is detected and automatically updated when possible. based on these measurements, the ifp calculates updated values for exposure time and sensor analog gains, whic h are sent to the sensor core through the communication bus. color correction is achieved through a linear transformation of the image with a 3 x 3 color correction matrix. color saturation can be adjusted in the range from zero (black and white) to 1.25 (125% of full color saturation). gamma correction compensates for nonlinear dependence of the display device output versus driving signal (monitor brightness versus crt voltage). output and formatting processed video can be output in the form of a progressive itu_r bt.656 or rgb stream. the itu_r bt.656 (default) stream contains 4 :2:2 data with optional embedded synchro- nization codes. this kind of output is typi cally suitable for subsequent display by stan- dard video equipment. for jpeg/mpeg compression, yuv/ encoding is suitable. rgb functionality is provided to support lcd devices. the mt9v131 can be configured to output 16-bit rgb (565rgb) and 15-bit rgb (555 rgb), as well as two types of 12-bit rgb (444rgb). the user can configure internal regi sters to swap odd and even bytes, chromi- nance channels, and luminance and chrominanc e components to facilitate interfacing to application processors.
mt9v131_ds rev. h 4/15 en 11 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor image flow processor figure 5: image flow processor block diagram the mt9v131 features smooth, continuous zo om and pan. this functionality is avail- able when the ifp output is downsized in the decimation block. the decimation block can downsize the original vga image to any integer size, including qvga, qqvga, cif, and qcif with no loss to the field of view. the user can program the desired size of the output image in terms of horizontal and vertical pixel count. in addition, the user can program the size of a region for downsizing. continuous zoom is achieved every time the region of interest is less than the entire vga image. the maximum zoom factor is equal to the ratio of vga to the size of the region of interest. for example, an image rendered on a 160 x 120 display can be zoomed by 640/ 160 = 480/120 = 4 times. continuous pan is achieved by adjusting the starting coordinates of the region of interest. also, a fixed 2x up-zoom is implemented by means of windowing down the sensor core. in this mode, the ifp receives a qvga-sized input data and outputs a vga-size image. the sub-window can be panned both vertically and horizontally by programming sensor core registers. the mt9v131 supports both led and xenon-ty pe flash light sources using a dedicated output pad. for xenon devices, the signal gen erates a strobe to fire when the imager's shutter is fully open. for led, the signal ca n be asserted or de-asserted asynchronously. flash modes are configured and engaged over the two-wire serial interface using ifp r0x98. image sensor gamma correction color correction demosaicing output formatting flash control ae, awb, flicker avoidance lens correction
mt9v131_ds rev. h 4/15 en 12 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor output data ordering output data ordering in ycbcr the first and second bytes can be swapped. luma/chroma bytes can be swapped as well. r and b channe ls are bit-wise swapped when chroma swap is enabled. see ifp r0x3a for channel swapping configuration. a bypass mode is available whereby raw bayer 10-bits data is output as two bytes. see ifp r0x08[7]. table 4: yuv/ycbcr output data ordering mode 1st byte 2nd byte 3rd byte 4th byte default (no swap) cb i y i cr i y i+1 swapped crcb cr i y i cb i y i+1 swapped yc y i cb i y i+1 cr i swapped crcb, yc y i cr i y i+1 cb i table 5: rgb output data ordering in default mode mode (swap disabled) byte d7 d6 d5 d4 d3 d2 d1 d0 565rgb firstr7r6r5r4r3g7g6g5 second g4 g3 g2 b7 b6 b5 b4 b3 555rgb first 0 r7 r6 r5 r4 r3 g7 g6 second g4 g3 g2 b7 b6 b5 b4 b3 444xrgb firstr7r6r5r4g7g6g5g4 secondb7b6b5b40000 x444rgb first 0 0 0 0 r7 r6 r5 r4 second g7 g6 g5 g4 b7 b6 b5 b4 table 6: byte ordering in 8 + 2 bypass mode byte ordering 8+2 bypass firstd9d8d7d6d5d4d3d2 second000000d1d0
mt9v131_ds rev. h 4/15 en 13 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor sensor core overview sensor core overview the sensor consists of a pixel array of 668 x 496 total, analog readout chain, 10-bit adc with programmable gain and black offset, and timing and control. figure 6: sensor core block diagram the sensor core?s pixel array is configured as 668 columns by 496 rows (shown in figure 7). the first 18 columns and the first 6 rows of pixels are optically black and can be used to monitor the black level. the last colu mn and the last row of pixels are also opti- cally black. the black row data is used internally for the automatic black level adjust- ment. there are 649 columns by 489 rows of optically active pixels, which provides a four-pixel boundary around the vga (640 x 480) image to avoid boundary affects during color interpolation and correcti on. the additional active column and additional active row are used to allow horizontally and vertically mirrored readout to also start on the same color pixel, as shown in figure 7. figure 7: pixel array description the sensor core uses the rgb bayer color pattern (shown in figure 8 on page 14). even- numbered rows contain green and red colo r pixels, and odd-numbered rows contain blue and green color pixels. even-numbered columns contain green and blue color pixels; odd- numbered columns contain red and green color pixels. active pixel sensor array control register analog processin g timing and control adc communication bus to ifp 10-bit data to ifp clock sync. signals (667,495) 18 black columns 1 black row 6 black rows (0, 0) 1 black column vga (640 x 480) + 4 pixel boundary for color correction + additional active column + additional active row = 649 x 489 active pixels
mt9v131_ds rev. h 4/15 en 14 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor sensor core overview figure 8: pixel color pattern detail (top right corner) the sensor core image data is read-out in a progressive scan. valid image data is surrounded by horizontal and vertical blan king, as shown in figure 9. the amount of horizontal and vertical blanking is progra mmable through the sensor core registers r0x05 and r0x06, respectively. line_valid is high during the shaded region of the figure. see ?appendix a ? sensor timing? on page 21 for the description of frame_valid timing. figure 9: spatial illustration of image readout notes: 1. do not change these registers. contact on semiconductor support for settings different from defaults. 2. ifp controls these registers when ae, awb, or flicker avoidance are enabled. pixel (18,6) (first optical clear pixel) black pixels column readout direction . . . . . . ... row readout direction g b g b g b r g r g r g g b g b g b r g r g r g g b g b g b r g r g r g g b g b g b p 0,0 p 0,1 p 0,2 .....................................p 0,n-1 p 0,n p 1,0 p 1,1 p 1,2 .....................................p 1,n-1 p 1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m-1,0 p m-1,1 .....................................p m-1,n-1 p m-1,n p m,0 p m,1 .....................................p m,n-1 p m,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 valid image horizontal blanking vertical blanking vertical/horizontal blanking
mt9v131_ds rev. h 4/15 en 15 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor electrical specifications electrical specifications the recommended operating temperature ran ges from ?20c to +70c. the sensor image quality may degrade above +40c. notes: 1. to place the chip in standby mode, first raise standby to v dd , then wait two master clock cycles before turning off the master clock. two master clock cycles are required to place the analog cir- cuitry into standby, low-power mode. 2. when standby is de-asserted, standby mode is ex ited immediately (within several master clocks), but the current frame and the next two frames will be invalid. the fourth frame will contain a valid image. table 7: dc electrical characteristics v dd = v aa = 2.8 0.25v; t a = 25 c definition symbol condition min typ max unit input high voltage v ih v dd - 0.25 v dd + 0.25 v input low voltage v il C0.3 0.8 v input leakage current i in no pull-up resistor; v in = v dd or d gnd C5.0 5.0 ? a output high voltage v oh v dd - 0.2 v output low voltage v ol 0.2 v output high current i oh 15.0 ma output low current i ol 20.0 ma tri-state output leakage current i oz 5.0 ? a analog operating supply current i aa default settings, c load = 10pf clkin = 12 mhz clkin = 27 mhz 10.0 10.0 20.0 20.0 25.0 25.0 ma digital operating supply current i dd default settings, c load = 10pf clkin = 12 mhz clkin = 27 mhz 5.0 10.0 8.0 15.0 20.0 20.0 ma analog standby supply current i aa standby stdby = v dd 0.0 2.5 5.0 ? a digital standby supply current i dd standby stdby = v dd 0.0 2.5 5.0 ? a
mt9v131_ds rev. h 4/15 en 16 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor electrical specifications notes: 1. for 30 fps operation with a 27 mhz clock, the user must have a precise duty cycle equal to 50%. with a slower frame rate and a slower clock, the clock duty cycle can be relaxed. 2. typical is 1/2 of clkin period. 3. pixclk can be programmed to be inverted or non-inverted. table 8: ac electrical characteristics v dd = v aa = 2.8 0.25v; t a = 25c definition symbol condition min typ max unit notes input clock frequency f clkin 101227mhz clock duty cycle 50:50 45 50 55 % 1 input clock rise time t r125ns input clock fall time t f125ns clkin to pixclk propagation delay low-to-high t plh p c load = 10pf 6 12 14 ns 3 high-to-low t phl p 61014ns pixclk to d out [7:0] at 27 mhz setup time t dsetup c load = 10pf 11 18 C ns 2 hold time t dhold 11 18 C ns pixclk to frame_valid and line_valid propagation delay low-to-high t plh f,l c load =10pf 4 9.0 13 ns high-to-low t phl f,l 47.513ns output rise time t out r c load =10pf 5 7.0 15 ns output fall time t out f c load =10pf 5 9.0 15 ns
mt9v131_ds rev. h 4/15 en 17 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor propagation delays propagation delays propagation delays for pixc lk and data out signals the output pixclk delay, relative to the mast er clock (clkin), is typically 10?12ns. note that the data outputs change on the rising ed ge of the master clock (clkin) as shown in in figure 10. pixclk by default is inverted from clkin but can be programmed to be non-inverted. figure 10: propagation delays for pixclk and data out signals note: default condition of th e ipa register r0x08[9] = 0. propagation delays for frame_valid and line_valid signals the line_valid and frame_valid signals chan ge on the same clock edge as the data output. the line_valid goes high on the same falling master clock edge as the output of the first valid pixel?s data and returns low on the same master clock falling edge as the end of the output of the last valid pixel?s data. the default timing of pixclk with respect to line_valid and frame_valid is shown in figure 11. figure 11: propagation delays for frame_valid and line_valid signals clk_in pixclk d out (7:0) d out (7:0) t oh t plh p t plh p t r t f d out (7:0) d out (7:0) d out (7:0) clkin frame_valid line_valid clkin frame_valid line_valid t plh f,l t phl f,l
mt9v131_ds rev. h 4/15 en 18 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor propagation delays output data timing as shown in figure 12, frame_valid goes high 6 pixel clocks prior to the time that the first line_valid goes high. it returns low at a time corresponding to 6 pixel clocks after the last line_valid goes low. figure 12: data output timing diagram notes: 1. pixclk = 27 mhz (max) 2. t fvsetup = / setup time for frame_valid before falling edge of pixclk / = 18ns 3. t fvhold = / hold time for frame_valid after falling edge of pixclk / = 18ns 4. t lvsetup = / setup time for line_valid before falling edge of pixclk / = 18ns 5. t lvhold = / hold time for line_valid after falling edge of pixclk / = 18ns 6. t dsetup = / setup time for d out before falling edge of pixclk / = 18ns 7. t dhold = / hold time for d out after falling edge of pixclk / = 18ns frame start: ff00 00a0 line start: ff00 0080 line end: ff00 0090 frame end: ff00 00b0 8. drawing shown has r0x08[9] = 1 pixclk frame_valid line_valid d out (7:0) t dsetup t dhold t fvhold t lvhold cb 0 y 1 cr 0 y last y last cb 0 cb 0 y 0 t fvsetup t lvsetup
mt9v131_ds rev. h 4/15 en 19 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor propagation delays figure 13: typical spectral characteristics figure 14: die center C image center offset note: not to scale. 0 5 10 15 20 25 30 35 40 45 50 350 450 550 650 750 850 950 1050 wavelength (nm) quantum efficiency (%) blue green red array array array array pixel (0, 0) die center - direction + direction + direction - direction 11.0um -91.3um 0 0 pixel array center
mt9v131_ds rev. h 4/15 en 20 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor propagation delays figure 15: chief ray angle (cra) vs. image height cra vs. image height plot image height cra (deg) (%) (mm) 000 5 0.112 1.46 10 0.224 2.92 15 0.336 4.38 20 0.448 5.84 25 0.560 7.30 30 0.672 8.75 35 0.784 10.21 40 0.896 11.67 45 1.008 13.13 50 1.120 14.59 55 1.232 16.05 60 1.344 17.51 65 1.456 18.97 70 1.568 20.43 75 1.680 21.89 80 1.792 23.34 85 1.904 24.80 90 2.016 26/26 95 2.128 27.72 100 2.240 29.18 mt9v131 cra design 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 cra (deg)
mt9v131_ds rev. h 4/15 en 21 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor appendix a C sensor timing appendix a C sensor timing figure 16: row timing and frame_valid/line_valid signals note: the signals in figure 16 are defined in table 9. note: in order to avoid flicker, frame time is 65.65ms. sensor timing is shown above in terms of ma ster clock cycle. the vertical blanking and total frame time equations assume that the number of integration rows (bits 11 through 0 of r0x09) is less than the number of active row plus blanking rows (r0x03 + 1 + r0x06 + 1). if this is not the case, the number of integration rows must be used instead to determine the frame time, as shown in table 10. table 9: frame time parameter name equation (master clocks) default timing at 12 mhz a active data time (r0x04 - 7) x 2 = 1,280 pixel clocks = 1,280 master clocks = 106.7 ? s p1 frame start blanking (r0x05 + 112) x 2 = 300 pixel clocks = 300 master clocks = 25.0 ? s p2 frame end blanking 14 clks = 14 pixel clocks = 14 master clocks = 1.17 ? s q horizontal blanking (r0x05 + 121) x 2 (min r0x05 value = 9) = 318 pixel clocks = 318 master clocks = 26.5 ? s a + q row time (r0x04 + r0x05 +114) x 2 = 1,598 pixel clocks = 1,598 master clocks = 133.2 ? s v vertical blanking (r0x06 + 9) x (a + q) + (q - p1 - p2) = 20,778 pixel clocks = 20,778 master clocks = 1.73ms nrows x (a + q) frame valid time (r0x03 - 7) x (a + q) - (q - p1 - p2) = 767,036 pixel clocks = 767,036 master clocks = 63.92ms f total frame time (r0x03 + r0x06 + 2) x (a + q) = 787,814 pixel clocks = 787,814 master clocks = 65.65ms table 10: frame time ? larger than one frame parameter name equation (master clocks) default timing v vertical blanking (long integration time) (r0x09 - r0x03) x (a + q) C f total frame time (long integration time) (r0x09 + 1) x (a + q) C p1 a q a q ap2 number of master clocks frame_valid line_valid ... ... ...
mt9v131_ds rev. h 4/15 en 22 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor serial bus description serial bus description registers are written to and read from the mt9v131 through the two-wire serial inter- face bus. the sensor is a serial interface slave and is controlled by the serial clock (sclk), which is driven by the serial interface master. data is transferred into and out of the mt9v131 through the serial data (s data ) line. the s data line is pulled up to 2.8v off- chip by a 1.5k ? resistor. either the slave or master device can pull the s data line down? the serial interface protocol determines which device is allowed to pull the s data line down at any given time. the registers are 16 bits wide and can be accessed through 16- bit or 8-bit two-wire serial bus sequences. protocol the two-wire serial interface defines several different transmission codes, as follows: ?a start bit ? the slave device eight-bit address. s addr is used to select between two different addresses in case of conflict with another device. if s addr is low, the slave address is 0x90; if s addr is high, the slave address is 0xb8. ? an acknowledge or a no-acknowledge bit ? an 8-bit message ?a stop bit sequence a typical read or write sequence begins by th e master sending a start bit. after the start bit, the master sends the slave device's 8-bi t address. the last bit of the address deter- mines if the request will be a read or a writ e, where a ?0? indicates a write and a ?1? indi- cates a read. the slave device acknowledges its address by sending an acknowledge bit back to the master. if the request was a write, the master then transfers the 8-bit register address to which a write should take place. the sl ave sends an acknowledge bit to indicate that the register address has been received. the master then tr ansfers the data 8 bits at a time, with the slave sending an acknowledge bi t after each 8 bits. the mt9v131 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. after 16 bits are transferred, the register address is automa tically incremented, so that the next 16 bits are written to the next register address. the master stops writing by sending a start or stop bit. a typical read sequence is executed as follows. first the master sends the write-mode slave address and 8-bit register address, just as in the write request. the master then sends a start bit and the read-mode slave address. the master then clocks out the register data 8 bits at a time. the master sends an acknowledge bit after each 8-bit transfer. the register address is auto-incremented after every 16 bits is transferred. the data transfer is stopped when the master sends a no-acknowledge bit. the mt9v131 allows for 8-bit data transfers through the two-wire serial interface by writing (or reading) the most significant 8 bits to the register and then writing (or reading) the least significant 8 bits to r0x7f (127). bus idle state the bus is idle when both the data and cloc k lines are high. control of the bus is initi- ated with a start bit, and the bus is released with a stop bit. only the master can generate the start and stop bits.
mt9v131_ds rev. h 4/15 en 23 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor serial bus description start bit the start bit is defined as a high-to-low transi tion of the data line while the clock line is high. stop bit the stop bit is defined as a low-to-high transi tion of the data line while the clock line is high. slave address the 8-bit address of a two-wire serial interfac e device consists of 7 bits of address and 1 bit of direction. a ?0? in the least signif icant bit (lsb) of the address indicates write mode, and a ?1? indicates read mode. the write address of the sensor is 0xb8, while the read address is 0xb9; this only applies when s addr is set high. data bit transfer one data bit is transferred during each clock pulse. the serial interface clock pulse is provided by the master. the data must be stable during the high period of the serial clock?it can only change when the two-wire se rial interface clock is low. data is trans- ferred 8 bits at a time, foll owed by an acknowledge bit. acknowledge bit the master generates the acknowledge clock pu lse. the transmitter (which is the master when writing, or the slave when reading) re leases the data line, and the receiver indi- cates an acknowledge bit by pulling the data line low during the acknowledge clock pulse. no-acknowledge bit the no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. a no-acknowledge bit is used to terminate a read sequence.
mt9v131_ds rev. h 4/15 en 24 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor two-wire serial interface sample write and read sequences (with saddr = 1) two-wire serial interface sample write and read sequences (with s addr = 1) 16-bit write sequence a typical write sequence for writing 16 bits to a register is shown in figure 17. a start bit given by the master, followed by the write address, starts the sequence. the image sensor will then give an acknowledge bit and expects the register address to come first, followed by the 16-bit data. after each 8-bits, the image sensor will give an acknowledge bit. all 16 bits must be written before the register will be updated. after 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register. the master stops writ ing by sending a start or stop bit. figure 17: timing diagram showing a write to r0x09 with value 0x0284 16-bit read sequence a typical read sequence is shown in figure 18. first the master has to write the register address, as in a write sequence. then a start bit and the read address specifies that a read is about to happen from the register. the master then clocks out the register data 8 bits at a time. the master sends an acknowledge bit after each 8-bit transfer. the register address is auto-incremented af ter every 16 bits is transferred. the data transfer is stopped when the master sends a no-acknowledge bit. figure 18: timing diagram showing a re ad from r0x09; returned value 0x0284 sclk s data start ack 0xb8 addr 0xb9 addr 0000 0010 r0x09 ack ack ack stop 1000 0100 nack sclk s data start ack 0xb8 addr 0xb9 addr 0000 0010 r0x09 ack ack ack stop 1000 0100 nack
mt9v131_ds rev. h 4/15 en 25 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor two-wire serial interface sample write and read sequences (with saddr = 1) 8-bit write sequence all registers in the camera are treated and accessed as 16-bit, even when some registers do not have all 16-bits used. however, cert ain hosts only support 8-bit serial communi- cation access. the camera provides a special accommodation for these hosts. to be able to write one byte at a time to th e register a special register address is added. the 8-bit write is done by first writing the upper 8 bits to the desired register and then writing the lower 8 bits to the special regi ster address (r0x7f). the register is not updated until all 16 bits have been written. it is not possible to just update half of a register. in figure 19, a typical sequence for 8-bit writing is shown. the second byte is written to the special register (r0x7f). figure 19: timing diagram showing a bytewise write to r0x09 with value 0x0284 8-bit read sequence to read 1 byte at a time, the same special register address is used for the lower byte. the upper 8 bits are read from the desired register. by following this with a read from the special register (r0x7f) the lower 8 bits are accessed, as shown in figure 20 the master sets the no-acknowledge bits. figure 20: timing diagram showing a bytewis e read from r0x09; returned value 0x0284 stop r0x7f ack start 0xb8 addr ack s data sclk ack ack ack ack r0x09 0xb8 addr 0000 0010 1000 0100 start start 0xb9 addr sdata sclk stop nack ack ack ack r0x09 start 0xb8 addr 0000 0010 start 0xb9 addr sdata sclk nack ack ack ack r0x7f start 0xb8 addr 1000 0100
mt9v131_ds rev. h 4/15 en 26 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor two-wire serial interface sample write and read sequences (with saddr = 1) two-wire serial bus timing the two-wire serial interface operation re quires a certain minimum of master clock cycles between transitions. these are specified below in master clock cycles. figure 21: serial host interface start condition timing figure 22: serial host interface stop condition timing note: all timing are in units of master clock cycle. figure 23: serial host interface data timing for write note: s data is driven by an off-chip transmitter. figure 24: serial host interface data timing for read note: s data is pulled low by the sensor, or allowed to be pulled high by a pull-up resistor off-chip. sclk 5 s data 4 sclk 5 sdata 4 sclk 4 sdata 4 sclk 5 sdata
mt9v131_ds rev. h 4/15 en 27 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor two-wire serial interface sample write and read sequences (with saddr = 1) figure 25: acknowledge signal timing after an 8-bit write to the sensor figure 26: acknowledge signal timing after an 8-bit read from the sensor note: after a read, the master receiver must pull down s data to acknowledge receipt of data bits. when read sequence is complete, the master must generate a no acknowledge by leaving s data to float high. on the following cycle, a start or stop bit may be used. sclk sensor pulls down sdata pin 6 sdata 3 sclk sensor tri-states sdata pin (turns off pull down) 7 sdata 6
mt9v131_ds rev. h 4/15 en 28 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor appendix b C overview of programming appendix b C overview of programming default sensor configuration in its default configuration, the sensor ou tputs up to 15 fps at 12 mhz master clock frequency. auto exposure, automatic white balance, 60hz flicker avoidance, defect correction, and automatic noise suppression in low-light conditions are enabled. the frame rate is controlled by ae and can be slowed down to 5 fps in low light. lens shading correction is disabled. gamma correction uses gamma = 0.6. image data are output in progressive ycbcr itu_r.bt.656 vga format, with y, cb, and cr values ranging from 16 to 240. the use of the non-default register settings shown in table 11 are recommended to opti- mize sensor performance in the above configuration. note: non-default register settings required for an optimal 30 fps, 27 mhz operation are shown in table 12. note: to obtain register settings for other frame rates and clock speeds, contact a on semiconductor fae. auto exposure target image brightness and accuracy of ae are set by ifp r0x2e[7:0] and r0x2e[15:8], respectively. for example, to overexpose images, set ifp r0x2e[7:0] = 0x78. to change image brightness on lcd in rgb preview mo de, use ifp r0x34[15:8]. ae logic can be programmed to keep the frame rate constant or vary it within certain range, by writing to ifp r0x37[9:5] one of the values tabulated in table 13. current and time-averaged luma values can be read in ifp r0x4c and r0x4d, respectively. the speed of ae is set using ifp r0x2f. the speed should be higher for preview modes and lower for video output to avoid sudden changes in brightness between frames. table 11: non-default register settings optimizing 15 fps at 12 mhz operation core: r0x5 = 0x2e, r0x7[4] = 0, r0x21 = 0xe401, r0x2f = 0xf7b6 ifp: r0x33 = 0x1411, r0x38 = 0x878, r0x39 = 0x122, r0x3b = 0x42c, r0x3e = 0xfff, r0x40 = 0x0e10, r0x41 = 0x1417, r0x42 = 0x1213, r0x43 = 0x1112, r0x44 = 0x7110, r0x45 = 0x7473 table 12: non-default register settings optimizing 30 fps at 27 mhz operation core: r0x05=0x84, r0x06=0xa, r0x07[4]=0, r0x21=0xe401 ifp: r0x33=0x1411, r0x39=0x122, r0x3b=0x42c, r0x3e=0xfff, r0x59=0x1f8, r0x5a = 0x25d, r0x 5c = 0x201e, r0x5d = 0x2725, r0x64 = 0x117d table 13: relation between ifp r0x37[9:5] setting and frame rate range minimum frame rate maximum frame rate = 15 fps maximum frame rate = 30 fps 30 fps n/a 4 15 fps 8 8 7.5 fps 16 16 5 fps 24 24
mt9v131_ds rev. h 4/15 en 29 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor appendix b C overview of programming auto exposure is disabled by setting ifp r0x06[14] = 0. when ae, awb, and flicker avoid- ance are all disabled (ifp r0x06[14] = 0, if p r0x06[1] = 0, and ifp r8[11] = 0), exposure and analog gains can be adjusted manually (see core registers r0x09, r0x0c, and r0x2b through r0x2e). automatic white balance awb can be disabled by setti ng ifp r0x06[1] = 0. use ifp r0x25[2:0] and r0x25[6:3] to speed up awb response. note that speeding awb up may result in color oscillation. if necessary, awb range can be restricted by changing the upper limit in ifp r0x25[14:8] and lower limit in ifp r0x25[6:0]. flicker avoidance use ifp r0x5b to choose automatic/manual, 50hz/60hz flicker avoidance and ifp r0x08[11] = 0 to disable this feature. flash for flash programming, see ifp r0x98 description. decimation, zoom, and pan for output decimation prog ramming, see ifp r0xa5 descri ption. table 14 provides some examples. note: for fixed 2x upsize zoom, set core r0x1e[0] = 1. interpolation use ifp r0x05[2:0] to adjust image sharpness. by default, sharpness is automatically reduced in low-light conditions (see ifp r0 x5[3]). for 565rgb 16-bit capture, set ifp r0x06[12] = 0 and ifp r0x05[3] = 0 to avoid contouring. special effects to switch from color to gray scale output, set ifp r0x08[5] = 1. image mirroring to mirror images horizontally, set core r0x20[14] = 1 and ifp r0x08[0] = 1. to flip images vertically, set core r0x20[15] = 1 and ifp r0x08[1] = 1. table 14: decimation, zoom, and pan ifp registers cif output (correct aspect ratio) qvga output 2:1 zoom qvga output 1:1 zoom r0xa5 26 160 0 r0xa6 586 320 640 r0xa7 352 320 320 r0xa8 0 120 0 r0xa9 480 240 480 r0xaa 288 240 240
mt9v131_ds rev. h 4/15 en 30 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor appendix b C overview of programming test pattern see ifp r0x48 and ifp r0x35[5:3] description. gamma correction see table 15 and table 16 for register settings required to setup non-default gamma correction. note that these se ttings determine output signal range. use ycbcr settings with itu_r btu-compatible devices. use yuv settings for jpeg capture and rgb preview; switching to yuv mode requires setting ifp r0x34 = 0 and ifp r0x35 = 0xff01. table 15: ycbcr settings gamma 0.45 0.5 0.55 0.6 (default) 0.7 1.0 ifp r0x53 0x3224 0x2a1d 0x2318 0x1e14 0x150d 0x804 ifp r0x54 0x5d44 0x543b 0x4c34 0x452d 0x3923 0x2010 ifp r0x55 0x987f 0x9277 0x8c70 0x8669 0x785d 0x6040 ifp r0x56 0xc0ae 0xbda9 0xbaa4 0xb7a0 0xb097 0xa080 ifp r0x57 0xe0d0 0xe0cf 0xe0cd 0xe0cc 0xe0c9 0xe0c0 table 16: yuv settings gamma 0.45 0.5 0.55 0.6 0.7 1.0 ifp r0x53 0x3829 0x3021 0x281b 0x2216 0x180f 0x0904 ifp r0x54 0x3021 0x6043 0x573b 0x4f34 0x4128 0x2412 ifp r0x55 0xad90 0xa687 0x9f7f 0x9877 0x8c69 0x6c48 ifp r0x56 0xdac5 0xd6c0 0xd3ba 0xcfb5 0xc8ab 0xb591 ifp r0x57 0xfeec 0xfeeb 0xfee9 0xfee7 0xfee4 0xfed9
mt9v131_ds rev. h 4/15 en 31 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor appendix b C overview of programming figure 27: 48- pin clcc package outline seating plane 4.4 11.43 5.215 5.715 lid material: borosilicate glass 0.55 thickness wall material: alumina ceramic substrate material: alumina ceramic 0.7 thickness 8.8 4.4 5.715 4.84 5.215 0.8 typ 1.75 0.8 typ 8.8 48 1 10.9 0.1 ctr 47x 1.0 0.2 48x r 0.15 48x 0.40 0.05 11.43 10.9 0.1 ctr lead finish: au plating, 0.50 microns minimum thickness over ni plating, 1.27 microns minimum thickness 2.3 0.2 1.7 note: 1. optical center = package center. first clear pixel optical center 1 c a b optical area optical area: maximum rotation of optical area relative to package edges: 1o maximum tilt of optical area relative to seating plane a : 50 microns maximum tilt of optical area relative to top of cover glass d : 100 microns a d 0.90 for reference only 1.400 0.125 0.35 for reference only v ctr ?0.20 a b c h ctr ?0.20 a b c image sensor die: 0.675 thickness 0.10 a 0.05 0.2 4x
mt9v131_ds rev. h 4/15 en 32 ?semiconductor components industries, llc,2015. mt9v131: 1/4-inch soc vga cmos digital image sensor revision history revision history rev. h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/16/15 ? updated ?ordering information? on page 2 rev. g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/31/15 ? converted to on semiconductor template rev. f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/4/11 ? updated trademarks ? applied updated template rev. e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/24/10 ? remove icsp reference from table 1, ?key performance parameters,? on page 1 and table 2, ?available part numbers,? on page 2 ? remove figure 4, figure 27, and figure 28 ? remove table 3 ? updated to non-confidential rev. d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/6/10 ? updated to aptina template rev. c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/1/08 ? changed operating temperature on table 1 on page 1 from ?20c to +60c to ?20c to +70c. ? changed register description for registers 48, 49, 50, 76, and 77 in table 8 (on page 14). ? added registers r0x1f, r0x20, r0x24, r0x2a, r0x30, r0x31, r0x32, r0x36, r0x37, r0x39, r0x3c, r0x3d, r0x3e, r0x46, r0x4 c, r0x4d, r0x59, r0x5a, r0x5c, r0x5d, r0x80, r0x81, r0x82, r0x83, r0x84, r0x85, r0x86, r0x87, r0x88, r0x89, r0x8a, r0x8b, r0x8c, r0x8d, r0x8e, r0x8f, r0x90, r0x91, r0x92, r0x93, r0x94, and r0x95 to table 9, ifp register description. ? updated figure 13: ?typical spec tral characteristics,? on page 19. ? added figure 15: ?chief ray angle (cra) vs. image height,? on page 20. ? added last sentence of first paragraph in ?auto exposure? on page 28. ? updated signal names to new standard: ?changed oe# to oe_bar ? changed reset# to reset_bar ? changed vaapix to v aa _pix rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3/5/07 ?fixed typos. ? updated document with hexadecimal format for registers. ? added table 3 on page 9 for clcc package. ? added figure on page 32 for clcc package. ? updated figure 10 on page 17, table 8 on page 16, and figure 12 on page 18. ? updated figure 13 on page 19. ? updated figure 17 on page 24.
on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillcs pr oduct/patent coverage may be accessed at www.onsemi.com/site/pdf/ patent-marking.pdf. scillc reserves the right to make changes without further noti ce to any products herein. scillc makes no warranty, representat ion or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaim s any and all liability, including without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data shee ts and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer a pplication by customers technical experts. scillc does not convey any license under its patent rights nor the rights of others. sc illc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such uninte nded or unauthorized applicatio n, buyer shall indemnify and hol d scillc and its officers, employ ees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly o r indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to a ll applicable copyright laws and is not for resale in any manner. mt9v131: 1/4-inch soc vga cmos digital image sensor revision history mt9v131_ds rev. h 4/15 en 33 ?semiconductor components industries, llc,2015 . rev. a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/06 ?initial release.

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